An insulated gate bipolar transistor (IGBT) is a semiconductor power device with a compositing structure that combines features of a metal-oxide-semiconductor field effect transistor (MOSFET) and a bipolar junction transistor (BJT). With the MOSFET's characteristic of easy control with a gate electrode, the bipolar current flow mechanism, and the advantages of shorter switching time and lower power loss, IGBTs have been widely applied in a high voltage and high power application.
In order to lower the on-resistance of the IGBT, field stop IGBTs have been developed. Field stop IGBTs generally have a (n-type) buffer layer at the bottom of the drift region and a thin implanted (p-type) collector region below the buffer layer. The collector region has a reduced number of charges compared to punch through IGBTs, and so has controlled minority carrier injection. The buffer layer acts as a field stop and terminates the electric field. For field stop IGBTs, it is important to carefully control the charge levels in the buffer layer and the collector layer.
Conventional technologies to configure and manufacture semiconductor power devices, particularly field stop IGBT devices, are still confronted with difficulties and limitations due to various tradeoffs and uncertainties in controlling the thickness and dopant concentration of the backside layers. In IGBT devices, there is a tradeoff between conduction loss and turn-off switching losses, Eoff. Conduction loss depends upon the collector to emitter saturation voltage Vce(SAT) at rated current. Greater carrier injection while the device is on improves the conductivity of the device, thus reducing conduction loss. Increased carrier injection would, however, cause higher turn-off switching losses because of energy dissipated in clearing out injected carriers during turn-off. However, for applications where switching losses do not dominate, greater carrier injection from the backside can reduce conduction loss and improve the collector to emitter saturation voltage Vce(SAT) at rated current. Examples of applications where switching losses do not dominate include, e.g., induction heating, and low frequency motor drives.
There are several conventional methods of manufacturing IGBTs with backside processing steps. In one implementation, the starting material is a single semiconductor substrate layer (such as N type) without an additional epitaxial layer atop. The top side processing steps are performed to form the IGBT structures on the top side of the substrate. After backside grinding, a backside N-type implant is performed to form an N-type buffer layer followed by a P-type implant to form the bottom P collector layer. A backside metal layer is formed to function as the drain/collector electrode. This process requires two backside implant operations and backside activation/anneal operation. In addition, the anneal processes on the backside layer can only be performed at a low temperature due to the limitations imposed by the already existing topside IGBT structures and metal layer. The laser anneal mitigates this by using short pulses of localized high temperatures on the wafer backside, which do not increase the wafer topside temperature substantially. However, laser anneal are typically shallow (typically on the order of 1 μm), and cannot anneal out the damages cause by the deeper N implant that is used to create the N buffer region.
An alternative implementation includes a starting material of an N-type substrate supporting an N-type epitaxial layer over it. The substrate is doped with volumetric doping concentration of the N-type buffer layer. After the topside processing steps to form IGBT structures on the top side of the substrate, the backside grinding is performed to reduce the lower N-type substrate layer to a predefined thickness. Ideally, the pre-defined thickness together with the volumetric doping concentration of the lower N-substrate layer result in the desired per area charge level of the buffer region. A bottom P-type layer is then formed from a backside P-type implant. A backside metal layer is in turn formed to function as the drain electrode. This implementation does not require a high temperature anneal after backside grinding for the N-type buffer layer because it is already doped as the starting lower substrate layer. However, these manufacturing processes encounter difficulties being unable to accurately control the backside grinding thickness with a tightly controlled tolerance. Variations in the thicknesses of N-type buffer layer vary charge levels in the N-type buffer layer and thus adversely affecting performance of the IGBT devices.
Another class of IGBT called the Reverse Conducting IGBT (RC-IGBT) are popular in the industry. These IGBTs combine the free-wheeling diode in the device structure, thereby eliminating the need for co-packaging a separate Diode chip with the IGBT. However, the conventional method for making RC-IGBT relies on a masking step on the wafer backside of a very thin wafer, after it has completed the topside process and has been background to 2 to 4 mil thickness. At such thicknesses, the silicon wafers are warped & difficult to handle which makes the process of masking extremely difficult.
It is within this context that embodiments of the present invention arise.